The present invention relates to a semiconductor chip, and a semiconductor device, and in particular, to a semiconductor chip capable of realizing reduction in cost when the semiconductor chip is mounted over a package substrate, miniaturization of the package substrate, and optimization of an interconnect pattern, and a semiconductor device.
It has lately been required to realize reduction in cost at the time of mounting a semiconductor chip over a package substrate, miniaturization of the package substrate, and optimization of an interconnect pattern.
In Japanese Unexamined Patent Publication No. 2006-41343, there has been disclosed a technology whereby respective solid-state image sensing devices identical to each other are provided with multiple pads to which an identical signal is coupled, thereby enabling the solid-state image sensing device to cope with multiple mounting configurations, and package configurations. FIG. 17 is a view showing the solid-state image sensing device disclosed in Japanese Unexamined Patent Publication No. 2006-41343. In FIG. 17, the solid-state image sensing device 631 includes an internal circuit 632 made up of transistors and so forth, a pad group 634 provided with pad opening metals 636 for use in coupling to the outside of the solid-state image sensing device 631, and a pad group 635. The pad group 634 and the pad group 635 are coupled to each other via the internal circuit 632, and a metal interconnect 633, and the pad group 634 and the pad group 635 include pads 637, and pads 638, respectively, the pads 637, 638 each being for use in receiving or outputting the identical signal
With the technology disclosed in Japanese Unexamined Patent Publication No. 2006-41343, the identical signal from the internal circuit 632 is supplied to the pads disposed along multiple sides of the solid-state image sensing device 631 through the metal interconnect 633. Accordingly, in the case of a signal for which it is necessary to secure a pad pitch at the time of wire bonding to a lead frame and so forth, if use is made of the pads with the identical signal coupled thereto, and disposed along different sides of the solid-state image sensing device 631, respectively, this will render it possible to secure the pad pitch that will be needed from a standpoint of mounting.
Further, in the case where mounting at small pitches is possible, including, for example, the case of using bumps and so forth, it is possible to suitably select a pad to be used from among the pads with the identical signal coupled thereto, rendering it possible to use, for example, the pads disposed along only one side of the device.
In Japanese Unexamined Patent Publication No. Hei05 (1993)-190674, there has been disclosed a technology related to a semiconductor chip in which the needs for rearranging respective positions of pads of the semiconductor chip do not arise even in the case of a change inn a direction in which an external lead is guided out when the semiconductor chip is mounted over a package provided with the external lead guided out of two sides thereof, opposite to each other, respectively. In Japanese Unexamined Patent Publication No. Hei02 (1990)-230749, there has been disclosed a technology related to a semiconductor chip in which a pad is disposed over one end face thereof, and a pad identical in function to the pad is also disposed over one other end face thereof, opposite to the one end face.
In Japanese Unexamined Patent Publication No. S63 (1988)-267598, there has been disclosed a technology related to a semiconductor device in which a semiconductor pellet with an integrated circuit formed therein is attached to an IC card substrate. With the technology disclosed in Japanese Unexamined Patent Publication No. S63 (1988)-267598, a bonding pad electrode provided over the surface of the semiconductor pellet is comprised of multiple first bonding pad electrodes disposed in a first disposition state, and multiple second bonding pad electrodes identical in function type to the first bonding pad electrodes, and disposed in a second disposition state differing in disposition state from the first disposition state. Further, either the plural first bonding pad electrodes, or the plural second bonding pad electrodes are electrically continuous with an external terminal lead corresponding thereto.
In Japanese Unexamined Patent Publication No. Hei11(1999)-67817, there has been disclosed a technology that is capable of coping with a package of a pellet-mount method including face-up type, and face-down type of identical semiconductor memories (pellets) without causing deterioration in memory performance, an increase in memory production cost, and package manufacturing cost. With the semiconductor memory (pellet) disclosed in Japanese Unexamined Patent Publication No. Hei11 (1999)-67817, an externally coupling electrode pad group having an identical function is disposed in both the first quadrant and the second quadrant of the pellet, the first quadrant and the second quadrant being divided by the center line of the a pellet. Further, an externally coupling electrode pad group having the identical function is disposed in either the third quadrant, or the fourth quadrant of the pellet, divided by the second center line of the pellet, orthogonal to the center line thereof. Furthermore, an externally coupling electrode pad group having the identical function is disposed inside the pellet center line having a width corresponding to half the length of a side of the pellet, orthogonal to the pellet center line.